module ALU(reset, clock, func, c_in, data, accu, c_out);

parameter size = 4;	// 4-Bit ALU

input reset;
input clock;
input [1:0] func;
input c_in;
input [size-1:0] data;

output c_out;
output accu;

reg [size-1:0] accu;
reg c_out;

always @ (posedge clock)
  if(reset == 0) begin
    accu <= 0;
    c_out <= 0;
  end else
    case(func)
      0 : begin			// Hold
      	    accu <= accu;
	    c_out <= 0;
	  end
      1 : begin			// Add
            {c_out, accu} <= accu + data + c_in;
	  end
      2 : begin			// Nand
      	    accu <= !(accu && data);
	    c_out <= 0;
	  end
      3 : begin			// Shift-Right
      	    c_out <= 0;
	    accu <= {accu[size-2:0], c_in};
	  end
    endcase
endmodule


module ALU_test;
  parameter size = 4;

  reg clock, reset;
  reg [1:0] func;
  reg c_in;
  reg [size-1:0] data;

  wire c_out;
  wire [size-1:0] accu;
  
  initial begin
    $monitor("reset=%b, function=%d, data=%d, c_in=%b, accu=%d, c_out=%b",
    	reset, func, data, c_in, accu, c_out);

    clock = 0;
    reset = 0;
    func = 0;
    c_in = 0;
    data = 0;

    #10 reset = 1;
    
    // add 1's
    #10 func = 1;
        data = 1;

    // shift
    #150 func = 3;
         data = 0;
    
    #200 $finish;
  end

  always begin
    #5 clock = !clock;
  end


  ALU a0(.reset(reset), .clock(clock), .func(func), .c_in(c_in), .data(data),
  	 .accu(accu), .c_out(c_out));
endmodule